A solid state device (SSD) controller interfaces with a flash device to read from and write to the flash device. A conventional solid state device (SSD) controller is often pad-limited. Flash devices, such as NAND flash (N-Flash) devices, have a large number of pin outs, and thus the SSD controller chip also requires a large number of pin outs to communicate with the flash devices. This large number of pin outs, and thus the large number of IO pads, can render the chip pad-limited. This problem is exacerbated when the SSD controller is configured to interface with a plurality of flash devices in parallel.
The pad-limitedness nature of a chip can be partially addressed using a staggered bond pad technology, which is shown in FIG. 1. This technology hinges on an observation that the bonding area (a metal strip that interfaces with an external bond wire) is often larger than the underlying pad body. The staggered bond pad technology fits more input output (IO) pads around a single perimeter ring by separating the bonding area and the IO pad body, and staggering the bonding area. FIG. 1 illustrates the staggered bond pad technology. FIG. 1 shows the IO pad bodies 10A-10D and the bonding areas 12A-12D. The bonding areas 12A-12D are decoupled from the corresponding pad bodies 10A-10D. While the staggered bond pad technology can be effective for fitting more pad bodies around the ring, this technology can be ineffective when the pad bodies themselves are large or when there is a large number of IO pads.